1. Field of Invention
Embodiments of the invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to nonvolatile memory devices and associated methods of operation.
A claim of priority is made to Korean Patent Application 2006-127270 filed on Dec. 13, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Two popular forms of flash memory devices include NAND flash memory devices and NOR flash memory devices. Compared with NAND flash memory devices, NOR flash memory devices typically have faster read times, slower write times, and a lower degree of integration. Due to these performance specifications, NOR flash memory devices are often used to provided storage for data that must be accessed quickly but is updated infrequently. For example, NOR flash memory devices are often used to provide storage for microcode in portable devices. On the other hand, due to its relatively higher storage and write performance, NAND flash memory devices are commonly used to provide mass data storage for devices such as digital cameras, PC cards, or even to replace hard disk drives.
In order to add even more data storage capacity to NAND flash devices, researchers have developed flash memory cells that are capable of storing more than one bit of data. Such memory cells are commonly referred to as “multi-level cells” and devices including multi-level cells are often referred to as multi-level cell (MLC) devices. As an example of a MLC, a two-bit flash memory cell can store two bits of data by varying the threshold voltage of the memory cell to four different states 11, 10, 01, and 00, which correspond to the data bits that they represent. The term “threshold voltage state” here denotes any threshold voltage with a value within a particular threshold voltage distribution. For example, FIG. 1 shows four different bell shaped threshold voltage distributions corresponding to four different threshold voltage states. The threshold voltage states represented in FIG. 1 provide an example of threshold voltage states that may be used in a two bit memory cell.
In FIG. 1, the leftmost threshold voltage distribution labeled “11” denotes an erased state of the memory cell. The memory cell is programmed by increasing its threshold voltage to change its threshold voltage state. Typically, such programming is accomplished by applying a program voltage (e.g., 14V-19V) to a control gate of the memory cell while grounding the channel of the memory cell. Under these bias conditions, a high electric field is formed between a floating gate of the memory cell and the channel, causing electrons to flow from the channel to the floating gate via an oxide film between the floating gate and the channel. Accumulation of electrons on the floating gate causes an increase in the memory cell's threshold voltage.
As illustrated in FIG. 1, a least significant bit (LSB) programming operation can be used to change the threshold voltage state of the memory cell from state “11” to state “10”. On the other hand, a most significant bit (MSB) programming operation can be used to change the threshold voltage state of the memory cell from state “11” to state “01” or from state “10” to state “00”.
FIG. 2 is a diagram illustrating read voltages used to determine the threshold voltage state of the two-bit memory cell during a read operation. Referring to FIG. 2, three different read voltages Vrd1, Vrd2, and Vrd3 can be used to distinguish between the four different threshold voltage states of the two-bit memory cell. Read voltage Vrd1 is set between −2.7 and 0.3 volts, read voltage Vrd2 is set between 0.7 and 1.3 volts, and read voltage Vrd3 is set between 2.3 and 2.7 volts.
In the read operation, the different read voltages are applied to the control gate of the memory cell while other voltages are applied to the source, drain, and channel of the memory cell. The threshold voltage state of the memory cell can be determined by measuring the amount of current that flows through the channel of the memory cell while each different read voltage is applied to the control gate. For simplicity of explanation, it will be assumed that when the level of the read voltage is less than the threshold voltage of the memory cell, no current will flow through the cell's channel. However, in practice the relationship between the read voltage, the threshold voltage, and the channel current in the memory cell may be more nuanced.
As an illustrative example, if current flows through the channel of the memory cell when read voltage Vrd1 is applied to the control gate, the threshold voltage of the memory cell is “11”. If no current flows through the channel of the memory cell when read voltage Vrd1 is applied to the control gate, but current flows through the channel of the memory cell when read voltage Vrd2 is applied to the control gate, the threshold voltage of the memory cell is “10”. If no current flows through the channel of the memory cell when read voltage Vrd2 is applied to the control gate, but current flows through the channel of the memory cell when read voltage Vrd3 is applied to the control gate, the threshold voltage of the memory cell is “01”. Finally, if no current flows through the channel of the memory cell when read voltage Vrd2 is applied to the control gate the threshold voltage of the memory cell is “00”.
In general, the threshold voltage states can be assigned to the different threshold voltage distributions in any arbitrary order. For example, the threshold voltage states could be reordered to increase in a gray coded order and so on. However, those skilled in the art will recognize that certain orderings of threshold voltage states have valuable characteristics. For example, in the illustrating of FIG. 2, one can determine whether or not the MSB of the memory cell is programmed simply by applying read voltage Vrd2 to the control gate and detecting the amount of current flowing through the channel of the memory cell. Such a process of using the one read voltage to determine the state of the MSB in a memory cell may be referred to as a MSB read algorithm. Similarly, a process of applying a combination of read voltages to determine the state of the LSB in a memory cell may be referred to as a LSB read algorithm.
FIG. 3 is a block diagram illustrating a conventional nonvolatile memory device, and FIG. 4 is a circuit diagram showing a structure of a memory cell array illustrated in FIG. 3.
Referring to FIG. 3, a conventional nonvolatile memory device 100 comprises a memory cell array 110, a row decoder 130, and a page buffer 140. Memory cell array 110 comprises a plurality of memory cells capable of storing data. Each of the memory cells is a multi-level cell that can store multiple bits of data. Memory cell array 120 further comprises a flag cell string 120 for storing store flag information indicating whether memory cells in each row have been programmed with MSB data (i.e., whether the memory cells have been “MSB programmed”).
As illustrated in FIG. 4, memory cell array 110 comprises a plurality of strings 111 connected to respective bit lines BL0-BLn. Each string 111 comprises a string select transistor SST, a ground select transistor GST, and memory cells MC0-MCm connected in series between select transistors SST and GST. The string select transistors SST in respective strings 111 are all connected to a string select line SSL, the ground select transistor GST in respective strings 111 are all connected to a ground select line GSL, and the memory cells MC0-MCm in respective strings 111 are all connected to corresponding word lines WL0-WLm.
Flag cell string 120 is connected to a flag bit line FBL, and has structure similar to strings 111. In particular, flag string 120 comprises a string select transistor SST, a ground select transistor GST, and flag cells MC0-MCm connected in series between select transistors SST and GST. The string select transistor SST in flag cell string 120 is connected to string select line SSL, the ground select transistor GST in flag cells string 120 is connected to ground select line GSL, and flag cells MC0-MCm are respectively connected to word lines WL0-WLm. Each of flag cells MC0-MCm in flag cell string 120 may store flag data indicating whether memory cells in a corresponding row (i.e., connected to the same word line) in memory cell array 110 have been programmed with MSB data.
Row decoder 130 controls the voltage levels of word lines WL0-WLm, string select line SSL, and ground select line GSL according to operating modes of the device. In FIG. 4, memory cell array 110 corresponds to one memory block; however, it could be expanded to comprise multiple memory blocks. Accordingly, row decoder 130 may perform a function of selecting a memory block and controlling word lines and select lines in the selected memory block. Page buffer 140 may be configured to read data from memory cell array 110 in a read operation and to program data into memory cell array 110 during a program operation. During a MSB program operation, a flag cell connected to a selected word line may be programmed with flag data via page buffer 140.
As described above, a nonvolatile memory device may determine whether memory cells in a selected row have been programmed with MSB data. This determination, in turn, can be used to inform an algorithm for reading data stored in the selected memory cells.
As illustrated in FIG. 4, one flag cell is used to store flag data for memory cells in each row of memory cell array 110. Unfortunately therefore, where the flag cell connected to a selected word line is defective or erroneous, it may be impossible to detect whether memory cells in the selected word line have been programmed with MSB data using the flag cell. This in turn may lead to read errors. In addition, the inability to determine whether a MSB program operation has been correctly performed may impair reading of LSD data. As a result, the reliability of the nonvolatile memory device as a whole may be impaired.